The re-use of circuit designs has become an important trend in the integrated circuit design industry. Companies may exchange or license design intellectual property (or “design IP”), typically including schematic and layout information for commonly used circuit blocks. The creation of a new integrated circuit may thus be greatly simplified by assembling pre-designed circuit blocks into a nearly complete system, with minimal new design effort required.
Verification is an important step in the process of designing and creating an electronic product. Verification helps ensure that the electronic design will work for its intended purpose, and is usually performed at several stages of the electronic design process. Circuit designers and verification engineers use different methods and analysis tools to verify circuit designs, including simulation. Simulation verifies a design by monitoring computed behaviors of the design with respect to test stimuli. Circuit performance measurements may be performed by a post-simulation engine that evaluates simulated circuit waveforms. A variety of commercially offered software programs are available for circuit simulation.
Digital and mixed-signal simulators support a concept known as a verification unit (or “vunit’” in Property Specification Language (PSL), or the System Verilog Assertions (SVA) “bindfile” equivalent). Verification units are containers of properties that describe the verification requirements of a circuit design. Verification units in the verification domain are thus rather analogous to modules or subcircuits, which are used to capture design information in the design domain. Verification units however capture verification information in a standalone entity or separate file from the circuit design itself During simulation, the contents of a verification unit may be considered alongside corresponding modules or subcircuits of a circuit design, sometimes on a per-instance basis. In analog design, verification is currently far more limited.
Low level analog and mixed-signal circuit operations are commonly verified during simulation by performing various device checks, such as checking that individual transistors are operating within their specified Safe Operating Area (SOA). More recently, a different level of simulator dynamic checking has evolved, known generally as circuit checks, in which the functionality of a group of devices or connectivity is checked all at once. Circuit checks may be run for example to look for high impedance nodes, DC leakage paths to ground, and other commonly occurring problems. Both static and dynamic types of checks are available in newer analog simulators. Analog functional block checking has also become enabled recently within some analog simulators, e.g., PSL and/or SVA temporal assertions may now be applied to analog circuit objects. All of the various types of checks used to verify circuit operation may be included in verification intellectual property (or “verification IP”).
Traditionally, analog verification using SPICE simulation has involved the creation of a single netlist file containing the circuit connectivity and the analysis statements (e.g., AC, DC, TRAN, etc.) to be run to produce output waveforms. Waveform post-processing may then verify the design. Newer generations of SPICE-type simulators now perform many of these verification checks more efficiently within the simulator itself. Even more recently, analog assertion checks have been introduced.
The netlist informs the simulator what needs to be checked, and how. In some tools, a user typically must manually edit the various checks and verification statements into the circuit netlist file produced by the design environment. Such hand editing requires simulator netlist language level skills, e.g., user understanding of the syntax and semantics of the checks to be performed, and is error prone. Syntactically, SPICE simulators require the checks to be specified as single statements, which may either be placed at the top level of the circuit hierarchy, or within subcircuit definitions (to bound their scope).
This verification approach made sense when there was just one check to be performed, or one type of check, but now there are many different types of checks, and often many instances of each check type. The result can be a netlist file that contains a plethora of check statements, often interspersed around the netlist file. Verification management has become a noticeable issue, with limitations making it difficult to add, disable, or remove checks after they have been initially created by a netlisting system.
A testbench-based approach could be extended to address such complexity. There are some major disadvantages to testbench level checks, however. For example, such an approach does not promote re-use of the verification IP beyond that immediate testbench. Testbench level checks also do not work when the block being checked is hierarchically integrated into a different context (e.g., when it is integrated as a component of a bigger circuit). Testbench based verification data may also get out of synch with the design, or may be lost entirely.
As a result, in current practice, analog verification IP does not naturally travel with the design block in an IP integration use scenario. Significant confusion may persist about what has been tested, and under what assumptions it has been tested. The process of analog design integration suffers as a result.
Thus a need exists for an improved approach to management of verification IP. Accordingly, the inventors have developed a novel way to help circuit designers create, store, and maintain verification IP for analog and mixed-signal circuit designs.